1. Field of the Invention
The present invention relates to reducing active leakage power in computer hardware and in particular to a method and system for active leakage power reduction in circuits using a dynamic power cutoff technique.
2. Description of Related Art
Leakage power is increasingly significant in CMOS circuits due to the exponential increase of subthreshold and gate leakage currents from technology scaling. Leakage power is becoming a major fraction of total VLSI chip power in active mode. Conventional leakage reduction techniques have been proposed. A forced stacking method reduces leakage power by inserting an extra serially connected transistor in the gate pulldown or pullup path and turning it off in standby mode, as described in M. Johnson, D. Somasekhar, and K. Roy, “Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS,” in Proc. of the Design Auto. Conf, pp. 442-445, June 1999. Input vector control uses the state dependence of leakage to apply a low leakage input vector to the circuit in standby mode to save leakage power, as described in J. Halter and F. Najm, “A Gate-Level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits,” in Proc. of the Custom Integrated Circuits Conf., pp. 475-478, 1997.
A conventional power cutoff technique, also referred to as supply gating, reduces leakage by disconnecting the global supply voltage in standby mode, as described in H. Kawaguchi, K. Nose, and T. Sakurai, “A Super Cutoff CMOS (SCC-MOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current,” IEEE J. of Solid State Circuits, vol. 35, pp. 1498-1501, October 2000. It inserts low Vt MOSFETs between the power connection of each logic gate and the global power line. Either pMOS or nMOS insertion is used to turn off either VDD or GND of the circuit during idle mode to save leakage power. FIG. 1 illustrates prior art pMOS system 10. When the pMOS cutoff transistor 12 is turned off, the subthreshold leakage reduces dramatically due to the stacking effect. Overall gate leakage also reduces because of a smaller voltage drop across gate oxides of transistors due to the dropped virtual VDD. Overall leakage power is dominated by subthreshold and gate leakages, so power cutoff is effective to reduce the deep submicron leakage power. One limitation is that data can be lost during the long sleep period due to the collapsed virtual VDD signal. The power cutoff transistors have about ˜6% extra delay in 0.3 μm CMOS, as described in M. Takahashi et al., “A 60-mw MPEG4 Video CODEC Using Clustered Voltage Scaling with Variable Supply-voltage Scheme,” IEEE J. of Solid-State Circuits, vol. 33, pp. 1772-1780, November 1998 and 3%-6% delay in 70 nm CMOS, as described in S. Bhunia, N. Banerjee, Q. Chen, H. Mahmoodi, and K. Roy, “A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating,” in Proc. of the Design Auto. Conf., pp. 479-484, June 2005. They also add chip area. One common shortcoming of the above-described techniques is that they can only reduce the circuit leakage power in standby mode.
Leakage is important in both standby and active operation modes. The leakage in active mode is significantly larger due to the higher die temperature in active mode. Accordingly, efficient leakage power reduction must target both standby and active leakage power. A dual Vth technique has been proposed which uses high-threshold voltage devices on noncritical paths to reduce leakage while using low-threshold devices on critical paths to maintain circuit speed as described in Z. Chen, C. Diaz, J. Plummer, M. Cao, and W. Greene, “0.18 μm Dual Vt MOSFET Process and Energy-Delay Measurement,” in Proc. of the 1996 Int'l. Electron Devices Meeting, pp. 851-854, December 1996 and L. Wei, Z. Chen, M. Johnson, K. Roy, and V. De, “Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits,” in Proc. of the Design Auto. Conf., pp. 489-494, June 1998. It reduces both active and standby leakage. However, this technique does not reduce the leakage on critical paths. Thus, it is it not advantageous for practical circuits, whose paths are usually well balanced. Supply voltage scaling, developed for switching power reduction, also reduces both active and standby leakage power, as described in M. Takahashi et al., “A 60-mw MPEG4 Video CODEC Using Clustered Voltage Scaling with Variable Supply-voltage Scheme,” IEEE J. of Solid-State Circuits, vol. 33, pp. 1772-1780, November 1998 and T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen, “A Dynamic Voltage Scaled Microprocessor System,” IEEE J. of Solid-State Circuits, vol. 35, pp. 1571-1580, November 2000. This technique has the shortcoming that level conversion is needed at the interface whenever an output from a low VDD unit drives a high VDD unit input. Another conventional approach proposed dynamic leakage reduction using supply gating, as described in S. Bhunia, N. Banerjee, Q. Chen, H. Mahmoodi, and K. Roy, “A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating,” in Proc. of the Design Auto. Conf., pp. 479-484, June 2005. This technique uses the Shannon expansion to identify the idle circuit parts and dynamically gate the supply to those parts to save active leakage power.
It is desirable to provide an improved active leakage power reduction method which targets the idle part of the circuit when it is in active mode.